A FinFET is a metal oxide semiconductor field effect transistor (MOSFET) formed on a semiconductor fin. A gate electrode is placed on at least two sides of a fin or is wrapped around the fin of the finFET. A channel is formed beneath the portion of the surfaces of the semiconductor fin under the gate electrode. A gate dielectric separates the gate electrode and the channel of the finFET. A double gate finFET employs a double gate configuration in which the gate electrode is placed on two opposite sides of the channel. In a triple gate finFET, the gate electrode is placed on one more side of a typically rectangular channel of the transistor. In a quadruple gate finFET or a wrapped gate finFET, the gate electrode is placed on four sides of the channel.
A gate electrode located on at least two sides of the channel of the transistor is a common feature of finFETs known in the art. The increased number of sides on which the gate electrode controls the channel of the finFET enhances the controllability of the channel in a finFET compared to a planar MOSFET. The improved control of the channel allows smaller device dimensions with less short channel effects as well as larger electrical current that can be switched at high speeds. A finFET device has faster switching times, equivalent or higher current density, and much improved short channel control than the mainstream CMOS technology utilizing similar critical dimensions.
In a typical finFET structure, at least one horizontal channel on a sidewall is provided within the semiconductor “fin” that is set sideways, or edgewise, upon a substrate. Typically, the fin comprises a single crystalline semiconductor material with a substantially rectangular cross-sectional area. Also typically, the height of the fin is greater than width of the fin to enable higher on-current per unit area of semiconductor area used for the finFET structure. In order to obtain desirable control of short channel effects (SCEs), the semiconductor fin is thin enough in a device channel region to ensure forming fully depleted semiconductor devices. Typically, the thickness, or the horizontal width, of a fin in a finFET is less than two-thirds of its gate length in order to obtain good control of the short channel effect.
In a typical double gate finFET, a gate dielectric layer and a gate conductor are located upon each of the two semiconductor fin sidewalls facing each other. A spacer material of substantial thickness is located between the top surface of the fin and the top portion of an inverted U-shaped gate electrode such that the top surface of the fin is not controlled directly by the portion of the gate electrode above it. In a typical triple gate finFET, a gate electrode of an inverted U shape is typically located upon the two semiconductor fin sidewalls and also upon the top surface of the fin structure. The top surface of the fin is separated from the top portion of the gate electrode only by a gate dielectric layer and is thus controlled by the gate electrode. In a quadruple gate finFET, a gate electrode surrounds a semiconductor fin having two sidewall surfaces, a top surface, and a bottom surface. Ion implantations are performed on the source and drain regions, which are the end portions of the semiconductor fin, to deliver halo, extension, and source/drain doping while using the gate electrode or other masking layer as a mask.
While providing improved MOSFET performance, the finFETs, however, pose unique design challenges. While planar MOSFET devices have virtually no limit on the width of the device as long as the width is above the lithographical minimum dimension, and therefore, the size of planar MOSFETs may be adjusted arbitrarily, typical finFETs have identical vertical height for the fins. While multiple finFETs may be wired in parallel to provide a transistor having a larger on-current, such transistors having a larger on-current can provide only integer multiples of a unit on-current of a discrete finFET. In other words, for the control of the on-current and the off-current of transistors, planar MOSFETs provide two continuously scalable parameters, which are the width, W and the length, L of the channel but finFETs provide only one continuously scalable parameter, which is the length, L of the finFET, since the height of the fin, and consequently the width of the channel is fixed for all finFETs. Therefore, for a given transistor length, L, which defines the ratio of the on-current to off-current, the amount of on-current from an individual fin is fixed. Use of multiple fins for a finFET may provide an on-current that is an integer multiple of the unit on-current, but non-integer fractions or non-integer multiples of the on-current of the unit on-current requires non-obvious or elaborate processing schemes and/or structures. Also, use of multiple fins tends to use more silicon surface area and makes the device design less area-efficient.
However, transistors with different on-currents are often required in the design of high performance integrated circuits. One such example is a six-transistor SRAM cell, wherein the beta ratio (the ratio of the on-current of a pull-down NFET to the on-current of a pass gate NFET) needs to be kept close to 2 for optimal performance of the SRAM cell.
Referring to FIG. 1, a layout of an exemplary prior art SRAM structure employing planar transistors is shown, which comprises a first pull-up p-type field effect transistor (PFET) 110, a second pull-up PFET 111, two pull-down n-type field effect transistors (NFETs) (120, 121), and two pass gate NFETs (130, 131). Each of the transistors (110, 111, 120, 121, 130, 131) comprises a portion of an active semiconductor area 103 and a portion of gate electrodes 104. The drains of one of the two pull-down NFETs (120, 121) and one of the first pull-up PFET 110 and the second pull-up PFET 111 are connected by M1 level metal lines 105. Of particular interest are the different widths of the active areas of the two pull-down NFETs (120, 121) and two pass gate NFETs (130, 131). It is necessary to maintain the ratio of on-currents between the two pull-down NFETs (120, 121) and two pass gate NFETs (130, 131) to a number close to 2 to maintain stability of an SRAM cell, hence the two different widths between the two types of NFETs.
Referring to FIG. 2, a circuit schematic for an exemplary prior art SRAM comprises a first pull-up PFET 306, a second pull-up PFET 306′, a first pull-down NFET 304, a second pull-down NFET 304′, a first pass gate NFET 302, and a second pass gate NFET 302′. The electrical connection between a first source/drain of the first pass gate NFET 302 and a first drain of the first pull-down NFET 304 is shown by a node 311, and the electrical connection between a second source/drain of the second pass gate NFET 302′ and a second drain of the second pull-down NFET 304′ is shown by a node 311′. The electrical connection between the drains of the first pull-up PFET 306 and the first pull-down NFET 304 and the gates of the second pull-up PFET 306′ and the second pull-down NFET 304′ is schematically shown by a line connecting them and nodes (313A, 313B) at the ends thereof. The electrical connection between the drains of the second pull-up PFET 306′ and the second pull-down NFET 304′ and the gates of the first pull-up PFET 306 and the first pull-down NFET 304 is schematically shown by a line connecting them and nodes (313A′, 313B′) at the ends thereof. Bit line wiring (315, 315′) is connected to the unwired source/drain of each of the pass gate NFETs (302, 303′). Word line wiring (317, 317′) is connected to each of the gates of the pass gate NFETs (302, 303′). The sources of the pull-up PFETs (306, 306′) are connected to a power supply wiring 39 and the sources of the pull-down NFETs (304, 304′) are connected to ground.
Design of an SRAM circuit employing finFET devices faces challenges due to the need to maintain the ratio of on-currents between pull-down NFETs and pass gate NFETs. Yang et al., “Fully Working 1.25 mm2 6T-SRAM cell with 45 nm gate length Triple Gate Transistors,” IEDM Tech. Dig., 2003, pp. 23-26 discloses an SRAM cell design in which a length of pass gate n-type finFET devices is drawn at a longer length of 100 nm to reduce the on-current of a finFET, while other finFET devices are drawn at a shorter length of 80 nm. By increasing the channel length of pass gate NFETs, the ratio of on-currents between the pull-down NFETs and the pass gate NFETs may be kept close to 2 and achieve SRAM cell stability.
Referring to FIG. 3A, a layout for an exemplary prior art SRAM structure employing finFETs is shown up to the M1 level. The layout for the exemplary prior art SRAM structure employing finFETs comprises a first pull-up p-type finFET 210, a second pull-up p-type finFET 211, two pull-down n-type finFETs (220, 221), and two pass gate n-type finFETs (230, 231). Each of the pull-up p-type finFETs and pull-down n-type finFETs (210, 211, 220, 221) comprises a portion of an active semiconductor area 216 and a portion of first gate electrodes 204 having a first width. Each of the pass gate n-type finFETs (230, 231) comprises a portion of an active semiconductor area 216 and a portion of second gate electrodes 204′ having a second width. The second width is greater than the first width, and is selected so that the ratio of on-currents between the pull-down n-type finFETs (220, 221) and the pass gate n-type finFETs (230, 231) is close to 2. The drains of one of the two pull-down NFETs (220, 221) and one of the first pull-up PFET 210 and the second pull-up PFET 211 are connected by M1 level metal lines 205.
Referring to FIGS. 3B and 3C, vertical cross-sectional views of a physical exemplary prior art SRAM structure based on the layout of FIG. 3A are shown. FIG. 3B and FIG. 3C are vertical cross-sectional views of the physical exemplary prior art SRAM structure based on the layout of FIG. 3A corresponding to a plane along the plane B-B′ and along the plant C-C′, respectively. The physical exemplary prior art SRAM structure comprises a semiconductor substrate 308 containing a handle substrate 301 and a buried insulator layer 302. Semiconductor fins 303 and gate caps 316 are formed in areas corresponding to the active semiconductor area 216 of the exemplary layout in FIG. 3A. A gate dielectric 315 is formed on two sidewalls of each of the semiconductor fins 303. A first physical gate electrode 304 corresponding to the first gate electrodes of the exemplary layout in FIG. 3A is formed on a physical pull-down n-type finFET, and a second physical gate electrode 304′ corresponding to the second gate electrodes of the exemplary layout in FIG. 3A is formed on a physical pass gate n-type finFET. The first physical gate electrode 30 and the second physical gate electrode 304′ contact both sidewalls of the semiconductor fins 303. The ratio of the on-currents of the n-type finFETs is controlled by the widths of the first physical gate electrode 30 and the second physical gate electrode 304′ in the direction perpendicular to the cross-sectional views.
While the prior art provides a method of providing SRAM cell stability by employing different channel lengths for various n-type finFETs, the use of the longer channel length not only consumes more silicon substrate area, but also introduces variables in terms of the variability of the physical dimensions of the gate lengths due to process variations and the complexities of optical proximity correction. For example, while the differences in dimension may be 20 nm between the longer length and the shorter length in a design layout, the differences in the physical dimension, which determines the actual device performance, is prone to process variations and optical proximity effect, i.e., the variability of actual dimensions due to adjacent physical structures in the layout. In addition, different gate lengths give different short channel effect, which can cause threshold voltage mismatching or ratio variation induced by Vdd variation.
Alternative approaches for providing multiple finFETs having different on-currents have also been proposed. For example, Aller et al., in U.S. Patent Application Publication No. 2004/0222477 A1 discloses a finFET device provided with a first semiconductor fin and a second semiconductor fin with different heights and adjustments on the ratio of the height of the first semiconductor fin to that of the second semiconductor fin are used to tune the performance of the transistor. However, the use of a thermal oxidation process to reduce the height of the fin requires that a hardmask be used in this process. Many processing steps are necessary such as deposition of a hardmask material, application and lithographic patterning of a photoresist, a transfer of a lithographic pattern into the hardmask, and thermal oxidation. The oxidation raises surface level due to volume expansion caused by the oxidation, which causes vertical variation in the height of the substrate which reduces usable depth of focus during subsequent lithographic process and may cause critical dimension (CD) variations in the printed lithographic images. Other prior art structures that provide multiple fin heights involve additional processes to enable multiple fin heights.
Therefore, there exists a need for a semiconductor structure having multiple finFET devices on the same semiconductor substrate, wherein the multiple finFET devices have the same fin height and different on-currents, and methods of manufacturing the same. Such structures may be advantageously employed in semiconductor circuits that require devices with different levels of on-currents.